1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device capable of stably generating an internal voltage even in a period before a complete power up.
2. Description of the Related Art
Many semiconductor devices such as dynamic random access memories (DRAMs) use not only power supply voltages (VDD, VSS and the like) supplied from the outside but also generate and se an internal voltage having a level different from that of a power supply voltage. Typically, an internal voltage is generated using a reference voltage corresponding to a target level of the internal voltage, an external power supply voltage VDD, and an external ground voltage VSS by charge pumping or voltage down converting.
In the case of a DRAM, an internal voltage generated using the charge pumping includes a boosting voltage VPP, a back bias voltage VBB, and the like. An internal voltage generated using the voltage down converting includes a core voltage VCORE, a bit line precharge voltage VBLP, and the like.
The boosting voltage VPP has a level higher than that of the external power supply voltage VDD and is mainly used to drive word lines. The back bias voltage VBB is a negative voltage lower than the ground voltage VSS and is mainly used as a body (bulk) bias of a cell transistor (a NMOS transistor).
FIG. 1 is a diagram illustrating a memory cell included in a semiconductor device according to the conventional art.
Referring to FIG. 1, the memory cell includes a cell transistor TR and a cell capacitor CP.
The cell transistor TR includes a NMOS transistor which is for forming a data transmission path SN between a bit line BL and the cell capacitor CP in response to the activation of a word line WL, provides a source-drain path between the bit line BL and the cell capacitor CP, and has a gate coupled to the word line WL. Accordingly, in order to form the data transmission path SN between the bit line BL and the cell capacitor CP, a boosting voltage VPP is supplied to the gate of the cell transistor TR.
Meanwhile, a power up operation indicates that a power supply voltage VDD has increased to a desired voltage level when a semiconductor device stably generates an internal voltage.
Accordingly, an internal voltage generation circuit of the semiconductor device generates an internal voltage in response to a power up control signal generated through the power up operation, and the internal voltage is initialized to a desired voltage level before the power up operation of a semiconductor device.
Specifically, in the memory cell of the semiconductor device as illustrated in FIG. 1, the data transmission path SN between the bit line BL and the cell capacitor CP is initialized to a ground voltage VSS. This is for substantially preventing latch up from occurring in the semiconductor device.
To this end, in the state in which the ground voltage VSS has been supplied to the bit line BL, a boosting voltage VPP is supplied to the word line WL to turn on the cell transistor TR, so that the ground voltage VSS of the bit line BL is transmitted to the data transmission path SN of the cell capacitor CP.
However, in the case of the conventional semiconductor device, before the power up operation, a node of the power supply voltage VDD and a node of the boosting voltage VPP are short-circuited to each other so that the power supply voltage VDD and the boosting voltage VPP have the same voltage level.
Therefore, even when the boosting voltage VPP is supplied to the word line WL before the power up operation, the cell transistor TR may not be sufficiently turned on.
Such a feature may occur more frequently in semiconductor devices in which the level of the power supply voltage VDD is reduced. Here, a latch up phenomenon may occur in the internal circuit of the semiconductor device and may damage the semiconductor device.